Altera Stratix GX Transceiver - Manual (Page 212)

8–8 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Design Examples
input inclk;
input rx_in;
output coreclk_out;
output tx_out;
output rx_bisterr;
output rx_bistdone;
output rx_clkout;
output reset;
wire reset_wire;
wire VCC;
assign reset = reset_wire;
assign VCC = 1;
//Altgxb Instantiation////////////////////////////
PRBS_BIST PRBS_BIST_inst(
.inclk(inclk),
.rx_in(rx_in),
.rx_slpbk(VCC),
.rxdigitalreset(reset_wire),
.coreclk_out(coreclk_out),
.rx_bistdone(rx_bistdone),
.rx_bisterr(rx_bisterr),
.rx_clkout(rx_clkout),
.tx_out(tx_out));
//Reset Module Instantiation//////////////////
reset_mod reset_mod_inst(
.clk(inclk),
.reset(reset_wire));
endmodule
Reset Module Design (reset_mod.v)
module reset_mod(clk, reset);
input clk;
output reset;
reg [19:0] counter;
reg reset;
always @ (posedge clk)
counter = counter +1;
always @ (counter) begin
if ((counter >= 20'b11111111111111100000) &&
(counter <= 20'b11111111111111111111))
reset = 1'b1;
else
reset = 1'b0;
end