Altera Stratix GX Transceiver - Manual (Page 276)

9–50 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
`timescale 1ns/10ps
module reset_seq_rx_rx_cruclk_rx_clkout (
rx_clkout,
rx_cruclk,
sync_reset,
async_reset,
receive_digitalreset,
rx_freqlocked,
rxanalogreset,
rxdigitalreset
);
input rx_cruclk; //Receive GXB input reference clock
input rx_clkout;//Receive recovered clock
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input receive_digitalreset; //Input : Reset the receiver section
input rx_freqlocked; //rx_freqlocked signal from receive;
Transition from 'lock to reference clock mode' to 'lock to data
mode'
output rxdigitalreset;//GXB Receive digital reset
output rxanalogreset;//Receive power down signal
reg rxdigitalreset;
reg rxdigitalreset_rx_cruclk;
reg rxdigitalreset_rx_clkout_Q;
reg rxanalogreset;
//Parameter value of T (2ms)based on the fastest clock (or 3.1875
Gbps)
parameter WAITSTATE_TIMER_VALUE = 1000000;
reg [19:0]waitstate_timer; //timer - for actual value, refer
stratix data sheet
//Receive Reset Sequence
always @(posedge rx_cruclk or posedge async_reset)
if(async_reset)
begin
rxanalogreset <= 1'b1;
rxdigitalreset_rx_cruclk <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;