Altera Stratix GX Transceiver - Manual (Page 140)

5–28 Altera Corporation
Stratix GX Transceiver User Guide January 2005
XAUI Mode Clocking
XAUI Inter-Transceiver Block Clocking
This section describes guidelines for the transceiver interface clocking
that is used inside the FPGA logic array when multiple transceiver blocks
are active. The transceiver blocks for each mode are supported by
transceiver-to-FPGA interface clocking, unique to the Stratix GX
transceiver. Different input and output clocks are available based on the
options provided by the Quartus II MegaWizard Plug-In Manager’s
built-in functions. The number of supported channels varies based on the
type of Stratix GX device you select (for example, EP1SGX40G,
EP1SGX25F, and so on). Consider the clocking schemes at a system level
with multiple lanes carefully to prevent pitfalls later in the design cycle.
XAUI mode is transceiver-block-based and can only support lanes in
multiples of four.
One of the clocking interfaces in the Stratix GX device is the interface
between the transceiver and the FPGA, which can be further divided into
FPGA-transmit of a transceiver and FPGA-receive of a transceiver. In
XAUI mode, depending on the options set in the MegaWizard Plug-In
Manager, you can use either the coreclk_out or tx_coreclk clock to
send the data into the transmit of the transceiver. However, the
tx_coreclk
must be frequency locked with the transmit system clock of
each transceiver block. (In each transceiver block, one transmitter PLL is
shared among four transmitters.)
In a multi-transceiver block scenario, if there are synchronous data
transfers based on transmit clocks when tx_coreclk is enabled for each
channel, each enabled transceiver block must connect to one of the
coreclk_out
outputs. When tx_coreclk is not enabled, the
Quartus II software automatically routes the coreclk_out signal to
write the clock of the phase compensation FIFO module using a global,
regional, or fast regional resource. In a multi-transceiver block
configuration, this feature can lead to timing violations because the
coreclk_out
per transceiver block cannot guarantee a phase
relationship. For this reason, Altera recommends clocking the
tx_coreclk
with a common clock for synchronous transmission.
In the multi-transceiver block case, use the transmit clock by enabling
tx_coreclk
and connecting one of the coreclk_out clock signals
output from one of the transceiver blocks that is active. An illustration of
this scheme is shown in
Figure 5–24 .