Altera Stratix GX Transceiver - Manual (Page 184)

6–30 Altera Corporation
Stratix GX Transceiver User Guide January 2005
GigE Mode Clocking
Figure 6–26. Inter-transceiver Line Connections for EP1SGX40G Device
PLD
Global
Clocks
IQ0 IQ1 IQ2
16
Transceiver Block 2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
Transceiver Block 3
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
Transceiver Block 0
/2
Transceiver Block 1
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
/2
TX PLL
IQ0
IQ1
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
IQ2
Transceiver Block 4
/2
4
4
4
4
4
refclkb
refclkb
refclkb
refclkb
refclkb
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs
4
Receiver
PLLs