Altera Stratix GX Transceiver - Manual (Page 170)

6–16 Altera Corporation
Stratix GX Transceiver User Guide January 2005
GigE Mode Transmitter Architecture
The transmitter phase compensation FIFO buffer is always used, and you
cannot bypass it. The input to the transmitter phase compensation FIFO
buffer is the data from the PLD logic array. The tx_ctrlenable and
tx_forcedisparity
signals are also passed through the FIFO buffer to
ensure that they are synchronized with the data when they feed to the
subsequent module.
GigE Transmitter Synchronization
The transmitter must send out the GigE synchronization sequence to
synchronize the target receiver. Stratix GX devices do not have a built-in
macro that performs this function on power-up or txdigitalreset.
This function must be implemented in user logic to send out a /K28.5/,
/Dx.y/
, /K28.5/, /Dx.y/, /K28.5/, /Dx.y/ sequence.
Figure 6–16 shows an example of the GigE synchronization pattern.
Although the example shows one D0.0 (8’h00) as the /Dx.y/ code, any
/Dx.y/
and any odd number of /Dx.y/ can be used.
Figure 6–16. Example of a GigE Synchronization Transmit Pattern
Idle Generation
In GigE mode, the transmitter replaces any /Dx.y/ code group following
a /K28.5/ comma with either a /D5.6/ (8’hc5) or a /D16.2/ (8’h50),
depending on the current running disparity, except when the data
following the /K28.5/ is /D21.5/ (8’hb5) or /D2.2/ (8’h42). This
replacement is to ensure the generation of /I1/ (
/K28.5/ , /D5.6/ ) and
/I2/ (/K28.5/, /D16.2/) ordered sets and to let the configuration
ordered sets /C1/ (/K28.5/, /D21.5/) and /C2/ (/K28.5/, /D2.2/)
be received. If the running disparity before the idle ordered set is positive,
an /I1/ is chosen. If the running disparity is negative, an /I2/ is chosen.
The disparity at the end of an /I1/ is the opposite of the disparity at the
beginning of the /I1/. However, the disparity at the end of an /I2/ is
clock
rx_out[7:0]
tx_ctrlenable
00 BC 00 BC 00 BC 00 8D A4
GigE Synchronization Pattern