Altera Stratix GX Transceiver - Manual (Page 13)

Altera Corporation 1–5
January 2005 Stratix GX Transceiver User Guide
Introduction
Channel Aligner
An embedded channel aligner aligns byte boundaries across multiple
channels and synchronizes the data entering the logic array from the
gigabit transceiver block’s four channels. The Stratix GX channel aligner
is optimized for a 10-Gigabit Ethernet XAUI 4-channel implementation.
The channel aligner includes the control circuitry and channel alignment
character detection defined by the XAUI protocol. The channel aligner is
only available in XAUI mode.
Rate Matcher
In multi-crystal environments, the clock frequencies of the transmitting
and receiving devices do not match. This mismatch can cause the data to
transmit at a rate slightly faster or slower than the receiving device can
interpret. The Stratix GX rate matcher resolves the frequency differences
between the recovered clock and the FPGA logic array clock by inserting
or deleting removable characters from the data stream, as defined by the
transmission protocol, without compromising transmitted data. If the
functional mode is XAUI, the rate matcher is based on the 10-Gigabit
Ethernet protocol. If the functional mode is GigE, the rate matcher is
based on the Gigabit Ethernet protocol.
Modes of
Operation You can bypass various modules of the gigabit transceiver block based on
the configured mode of operation. Stratix GX transceivers currently
support basic mode, SONET mode, and XAUI mode. This section
provides an overview of each supported mode of operation.
Basic Mode
Basic mode enables a subset of the transceiver blocks so you can perform
customizable configuration. Channel aligner and the rate matcher
features are not available in this mode. Refer to the Basic Mode chapter for
more details on the configurability of this mode.
Figure 1–2 shows a block
diagram of a duplex channel configured in basic mode.