Altera Stratix GX Transceiver - Manual (Page 19)

Altera Corporation 2–1
January 2005
2. Stratix GX Analog
Description
Introduction This chapter describes how to serialize the parallel data for transmission
and convert received data into parallel data. Data transmission and
reception is performed by pseudo current mode logic (PCML) buffers.
These transceiver buffers support programmable pre-emphasis,
equalization, and programmable V
OD
settings in I/O buffers.
The programmable pre-emphasis setting is available on transmit buffers
to maximize the eye opening on the far-end receiver by boosting the
high-frequency component of the data signal. Similarly, programmable
equalization is available for receive buffers to reduce the high-frequency
losses and inter-symbol interference. These features are useful in lossy
transmission lines. Transceivers also support flexible reference clock
generation capabilities, including a dedicated transmitter phase-locked
loop (PLL) and four receiver PLLs per transceiver block.
The clock recovery unit (CRU) is the main part of each receive analog
section; it recovers the clock from the serial data stream (see
Figure 2–1 ).
You can set the CRU to automatically or manually alter the receiver PLL
phase and frequency to match the bit transition on the incoming data
stream. This is to eliminate any clock-to-data skew or to keep the receiver
PLL locked to the reference clock (lock-to-data or lock-to-reference
mode).
During the clock recovery phase, the receiver PLL initially locks to the
reference clock and then attempts to lock on to the incoming data by first
recovering the clock from the incoming serial data.