Altera Stratix GX Transceiver - Manual (Page 166)

6–12 Altera Corporation
Stratix GX Transceiver User Guide January 2005
GigE Mode Receiver Architecture
Reset
The rxdigitalreset signal governs the reset condition of the 8B/10B
decoder. In reset, the disparity registers are cleared. Upon exiting reset,
the 8B/10B decoder starts with either a positive or negative disparity. The
decoder calculates the initial running disparity based on the first valid
code that is received.
The receiver block must be word-aligned after reset before the 8B/10B
decoder can decode valid data or control codes.
Code Error Detect
The rx_errdetect signal indicates when the code received contains an
error. This port is optional and, if not in use, there is no way to detect
whether a code received is valid. The rx_errdetect goes high if a code
received is an invalid code, or if it has a disparity error. If a code is
received that is not part of the valid Dx.y or Kx.y list, the
rx_errdetect
signal goes high. This signal is aligned to the invalid
code word received at the PLD logic array.
Disparity Error Detector
The 8B/10B decoder detects disparity errors based on which 10-bit code
it received. The disparity error is indicated at the optional rx_disperr
port. The current running disparity is based on the disparity calculation
of the last code received. The disparity calculation is described in the
8B/10B code section in the Appendix.
If negative disparity is calculated for the last 10-bit code, a neutral or
positive disparity 10-bit code is expected. If the decoder does not receive
a neutral or positive disparity 10-bit code, the rx_disperr signal goes
high.
If a positive disparity is calculated, a neutral or negative disparity 10-bit
code is expected. In this situation, the rx_disperr signal goes high if the
code received is not as expected. When the rx_disperr signal is high,
the rx_errdetect signal also goes high.
Figure 6–13 shows a case where the disparity is violated. A K28.5 code
has an 8-bit value (8’hbc) and a 10-bit value (jhgfiedcba). The 10-bit
value is 10’b0011111010 (10’h17c) for RD- or 10’b1100000101
(10’h283) for RD+. If the running disparity at time n – 1 is negative the
expected code at time n must be from the RD- column. Because a K28.5
does not have a balanced 10-bit code (having an equal number of 1’s and
0’s), the expected RD code must toggle back and forth between RD- and
RD+
. At time n + 3, the 8B/10B decoder received an RD+ K28.5 code
(10’h283), which would make the current running disparity negative.