Altera Stratix GX Transceiver - Manual (Page 59)

Altera Corporation 3–13
January 2005 Stratix GX Transceiver User Guide
Basic Mode
Byte Deserializer
The byte deserializer module further reduces the speed at which the
FPGA logic array must run in order to meet performance. If the input is
10 bits of data, the output to the FPGA logic array is deserialized to 20
bits. If the input is 8 bits of data, the output to the FPGA logic array is
deserialized to 16 bits. The byte deserializer does not process the data and
as such, the control signals that are fed to the module are only processed
to match the latency to the data.
The byte deserializer in the receiver block takes in a maximum of 13 bits.
It is possible to feed the following to the byte deserializer:
■ 8 bits of data and up to three control signals (rx_patterndetect,
rx_syncstatus
, and rx_a1a2sizeout)
■ 8 bits of data and up to five control signals (rx_patterndetect,
rx_syncstatus
, rx_disperr, rx_ctrldetect, and
rx_errdetect )
■ 10 bits of data and up to two control signals (rx_patterndetect
and rx_syncstatus)
The byte deserializer outputs up to 26 bits, depending on the number of
bits that was passed to it. When the input includes data and control
signals, the data and the control signals are deserialized to include double
the data bits and two bits of each control signal, one for the MSB and one
for the LSB. The aggregate bandwidth does not change by using the byte
deserializer, because the logic array data width is doubled.
Figure 3–11 demonstrates input and output signals of the byte
deserializer when deserializing a 10-bit data input to 20 bits. In this case,
the alignment pattern A (1010100000) is located in the MSB of the 20-bit
output, and this is reflected with patterndetect [1] going high. The
output of the byte deserializer is AX, CB, ED, and so on.