Altera Stratix GX Transceiver - Manual (Page 313)

Altera Corporation C–3
January 2005 Stratix GX Transceiver User Guide
Quartus II Software Messages
The following sections provide details on the feedback provided by the
various versions of the Quartus II software when the design contains
configurations
1 , 2 , or 3 , described previously.
Quartus II Software to Version 3.0 SP2
This version of the Quartus II software allows configurations 1 , 2 , and 3 ,
and provides no warnings. Because the behavior of the configuration is
not modeled, differences in functionality exist between simulations and
actual silicon.
Altera ® recommends that you do not run the reset controller off the clock
from the REFCLKB pin. This might result in the signals to the GXB being
deasserted asynchronously (with respect to the clocks from the GXB).
However, a serial link usually goes through an initialization phase.
Therefore, metastability issues might not be critical because the logic has
enough time to recover during initialization.
Quartus II Software Version 4.0
For configurations 1 and 2 , the Quartus II software version 4.0 prevents
the .sof file from being generated.
■ The assembler (ASM) will have an internal error (IE). Here are some
of the messages from the Quartus II software log:
● Internal Error: Sub-system: ASM, File: asm_cdr.cpp, Line: 839,
Illegal Clock Placement. Problem between Quad PLL and the
Quad Clock Pad. PLL has Enable connected
● Internal Error: Sub-system: ASM, File: asm_cdr.cpp, Line: 840,
Illegal Clock Placement. Problem between Quad PLL and the
Quad Clock Pad. PLL has Reset connected
● Internal Error: Sub-system: ASM, File: asm_cdr.cpp, Line: 863,
Illegal Clock Placement. Problem between RX Channel Resets
and the Quad Clock Pad. All RXs in Quad have Resets
connected
f
Please refer to recommendation n in “Recommendations” on page C–5 if
you have an existing design (including the board) and cannot make
changes.
The Quartus II software version 4.0 supports configuration 3 . There are
no warnings and results vary from simulation to actual silicon.