Altera Stratix GX Transceiver - Manual (Page 73)

Altera Corporation 3–27
January 2005 Stratix GX Transceiver User Guide
Basic Mode
Figure 3–23. Inter-Transceiver Line Connections for EP1SGX25 Device
16
IQ0 IQ1 IQ2
Transceiver Block 0
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
IQ2
/2
4 4
Receiver
PLLs
Transmitter
PLL
PLD Global Clocks
Transceiver Block 1
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
IQ2
/2
4 4
Receiver
PLLs
Transmitter
PLL
Transceiver Block 2
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
IQ2
/2
4 4
Receiver
PLLs
Transmitter
PLL
Transceiver Block 3
IQ0
IQ1
Global Clocks, I/O Bus, General Routin g
Global Clocks, I/O Bus, General Routin g
IQ2
/2
4 4
Receiver
PLLs
Transmitter
PLL
refclkb
refclkb
refclkb
refclkb