Altera Stratix GX Transceiver - Manual (Page 235)

Altera Corporation 9–9
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
always @ (posedge inclk or posedge async_reset) begin
if (async_reset)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <= WAITSTATE_TIMER_VALUE;
state <= STROBE_TXPLL_LOCKED;
end
else
case (state)
IDLE:
if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state <= STROBE_TXPLL_LOCKED;
end
else
begin
rxdigitalreset_inclk <= 1'b0;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
state <= IDLE;
if(transmit_digitalreset)
txdigitalreset <= 1'b1;
else
txdigitalreset <= 1'b0;
end
STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset
can be asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
//Wait untill the TXPLL is locked to inclk and TX PLL has a
stable output clock which is also fed to RX CRU
else if (pll_locked)
begin
state <= STABLE_TX_PLL;
rxdigitalreset_inclk<= 1'b1;
rxanalogreset_inclk <= 1'b0;
txdigitalreset<= 1'b0;
pll_areset <= 1'b0;
end
else
begin