Altera Stratix GX Transceiver - Manual (Page 230)

9–4 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
Recommended
Resets The following reset recommendations help guard against potential
initialization issues during the training of the transmitter PLL and
receiver PLLs. The counters that you specify in the recommendations
filter out any high frequency effects to ensure that the lock signals are
stable before releasing the subsequent reset signals. This action adds to
the robustness of the reset sequence.
Receiver & Transmitter Reset
The configurations and design examples in this section describe how to
implement a reset sequence for both the receiver and transmitter
channels. The designs in this section demonstrate the reset sequence only.
Each design example lists the constraints specific to the example to help
you understand the design parameters and limitations. You may want to
add additional escape states and other system-specific features in your
design. If your design requirements and GXB configurations are different
(for example, usage for multiple transceivers) from the design example,
you can make necessary changes using the flow chart and waveform
figures in each section as guidelines.
Train Receive CRU With Transmit PLL Output Clock
This section contains RTL examples that show some scenarios where a
transceiver is programmed to duplex and the transmitter PLL output
clock trains the receiver clock recovery unit (CRU).
Figure 9–2 shows the possible options on clocking the transmit and
receive parallel interface for a selected data path width.
Figure 9–2. Receiver & Transmitter Clock Options
Transmit & Receive (Duplex)
with Train RX CRU with TXPLL
Output Clock
rx_clkout
Single Width
(8/10)
Double Width
(16/20)
Data Path Width
rx_coreclk tx_coreclk inclk rx_clkout tx_coreclk inclk
Transmit
Parallel Clock
Transmit
Parallel Clock
Receive
Parallel Clock
Receive
Parallel Clock