Altera Stratix GX Transceiver - Manual (Page 117)

Altera Corporation 5–5
January 2005 Stratix GX Transceiver User Guide
XAUI Mode
Figure 5–3. Block Diagram of a Duplex Channel Configured in XAUI Mode
XAUI Mode
Receiver
Architecture Figure 5–4 diagrams the digital components of the receiver in XAUI
mode.
Figure 5–4. Block diagram of Receiver Digital Components in XAUI Mode
Analog Section Digital Section
Deserializer
Byte
Serializer
Phase
Compensation
FIFO Buffer
Serializer
8B/10B
Encoder
Receiver
Transmitter
Reference
Clock
Word
Aligner
Channel
Aligner Rate
Matcher 8B/10B
Decoder
Reference
Clock
Phase
Compensation
FIFO Buffer
Transmitter
PLL
Receiver
PLL
Clock
Recovery Unit
Byte
Serializer
Analog Section Digital Section
Deserializer
Reference
Clock
Word
Aligner
Channel
Aligner Rate
Matcher 8B/10B
Decoder
Phase
Compensation
FIFO Buffer
Byte
Serializer
Receiver
PLL
Clock
Recovery Unit
Receiver