Altera Stratix GX Transceiver - Manual (Page 250)

9–24 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
output rxdigitalreset;//GXB Receive digital reset
output rxanalogreset;//Receive power down signal
output txdigitalreset; //GXB transmit digital reset
output pll_areset;//GXB power down signal
reg rxdigitalreset;
reg txdigitalreset;
reg pll_areset;
reg [2:0] state;
reg rxdigitalreset_rx_cruclk;
reg rxdigitalreset_rx_coreclk_Q;
reg rxanalogreset;
parameter IDLE = 3'b000;
parameter STROBE_TXPLL_LOCKED = 3'b001;
parameter STABLE_TX_PLL = 3'b010;
//Parameter value of T (2ms)based on the fastest clock (or 3.1875
Gbps)
parameter WAITSTATE_TIMER_VALUE = 1000000;
reg [19:0]waitstate_timer; //timer - for actual value, refer
stratix data sheet
//Transmit Reset Sequence
always @ (posedge inclk or posedge async_reset) begin
if (async_reset)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state <= STROBE_TXPLL_LOCKED;
end
else
case (state)
IDLE:
if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
state<= STROBE_TXPLL_LOCKED;
end
else
begin
pll_areset <= 1'b0;
state <= IDLE;
if(transmit_digitalreset)
txdigitalreset <= 1'b1;
else
txdigitalreset <= 1'b0;
end