Altera Stratix GX Transceiver - Manual (Page 240)

9–14 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
reg rxdigitalreset_rx_clkout_Q;
reg rxanalogreset_rx_clkout_Q;
parameter IDLE = 3'b000;
parameter STROBE_TXPLL_LOCKED = 3'b001;
parameter STABLE_TX_PLL = 3'b010;
parameter WAIT_STATE = 3'b011;
//Parameter value of T (2ms)based on the fastest clock (or 3.1875
Gbps)
parameter WAITSTATE_TIMER_VALUE = 1000000;
reg [19:0]waitstate_timer; //timer - for actual value, refer
stratix data sheet
assign rxanalogreset = rxanalogreset_inclk;
always @ (posedge inclk or posedge async_reset) begin
if (async_reset)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <= WAITSTATE_TIMER_VALUE;
state <= STROBE_TXPLL_LOCKED;
end
else
case (state)
IDLE:
if (sync_reset) //Synchronous Reset can be
asserted in IDLE state (After reset seq has finished)
begin
rxdigitalreset_inclk <= 1'b1;
rxanalogreset_inclk <= 1'b1;
txdigitalreset <= 1'b1;
pll_areset <= 1'b1;
waitstate_timer <=
WAITSTATE_TIMER_VALUE;
state<= STROBE_TXPLL_LOCKED;
end
else
begin
rxdigitalreset_inclk <= 1'b0;
rxanalogreset_inclk <= 1'b0;
pll_areset <= 1'b0;
state <= IDLE;
if(transmit_digitalreset)
txdigitalreset <= 1'b1;
else
txdigitalreset <= 1'b0;
end
STROBE_TXPLL_LOCKED: if (sync_reset) //Synchronous Reset
can be asserted in IDLE state (After reset seq has finished)