Altera Stratix GX Transceiver - Manual (Page 97)

Altera Corporation 4–15
January 2005 Stratix GX Transceiver User Guide
SONET Mode
The coreclk_out is the output from the transmitter PLL. A
coreclk_out
is available for each transceiver block that is used. Altera ®
recommends clocking the logic that is feeding the transmitter with this
clock.
The read clock of the receiver phase compensation FIFO module and the
write clock of the transmitter phase compensation FIFO module are
optionally enabled to manually feed in a clock from the FPGA logic array.
You use these options to optimize the global clock usage. For instance, if
all transmitter channels between transceiver blocks are from a common
clock domain, the transceiver instantiations use a total of one global
resource clock versus one global per transceiver block, if the
tx_coreclk
option is not enabled.
The same situation can be optimized for the receiver channels in a single
crystal synchronous system with the rx_coreclk. Even in a system that
is based on a single crystal, the recovered clock can still become
asynchronous to the system clock during initialization or long run
lengths. As a result, the pointers of the Receiver Phase Compensation
FIFO module might overlap and fail to function correctly. In situations
where there are long run lengths or no data transmissions, these FIFO
modules must be reset by the rxdigitalreset signal.
In multi-crystal environments, individual recovered clocks must drive
the read clock of the phase compensation FIFO module. The Quartus
® II
software does this by default, and you do have to manually make this
connection. The rx_coreclk and tx_coreclk must be frequency
matched with their respective read and write ports. The phase
compensation FIFO module can only correct for phase, not frequency
differences.
Figure 4–13 shows the clock configuration with these
optional input ports enabled.