Altera Stratix GX Transceiver - Manual (Page 68)

3–22 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Basic Mode Clocking
This configuration has an independent rx_cruclk that feeds the
receiver PLL reference clock. This input clock port is only available when
the receiver PLL is not trained by the transmitter PLL. There is one
rx_cruclk
associated with a channel. If four channels are active, there
are four rx_cruclk signals.
The RX_CLKOUT is the recovered clock from the associated receiver
channel. One rx_clkout is available for each receiver channel that is
used. You can use this clock to clock the rate-matching FIFO buffer write
port in the device. The read port of the FIFO buffer can be clocked by the
CORECLK_OUT
signal or device clock.
The CORECLK_OUT port is the output from the transmitter PLL. A
CORECLK_OUT
port is available for each transceiver block used. You
should use the CORECLK_OUT clock to clock the transmitter input.
The receiver phase compensation FIFO buffer read clock and the
transmitter phase compensation FIFO buffer write clock can be optionally
enabled to manually feed in a clock from the device buffer write block.
You can use these options to optimize the global clock usage. For
example, if all transmitter channels between transceiver blocks are from
a common clock domain, the transceiver instantiations use only one
global resource clock instead of one global per transceiver block, if the
TX_CORECLK
option is disabled.
The situation is similar for the receiver channels in a single-crystal
synchronous system with RX_CORECLK. During initialization or long run
lengths, the recovered clock becomes asynchronous with the system
clock. As a result, the pointers of the receiver phase compensation FIFO
buffer might overlap and fail to function correctly. In these situations, the
receiver phase compensation FIFO buffers must be reset by the
rxdigitalreset
signal.
In multi-crystal environments, individual recovered clocks must drive
the read clock of the phase compensation FIFO buffer. The Quartus
® II
software does so by default and you do not need to manually make this
connection. The rx_coreclk and tx_coreclk must be frequency
matched with their respective read and write ports.
Figure 3–21 shows
the clock configuration with these optional input ports enabled.