Altera Stratix GX Transceiver - Manual (Page 34)

2–16 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Receiver Analog
Valid receiver bandwidth settings are low, medium, and high. The –3-dB
frequencies for these settings vary due to the non-linear nature and data
dependencies of the circuit. You vary the bandwidth to customize the
performance on specific systems.
Clock Recovery Unit
The CRU in each Stratix GX receiver channel recovers the clock from the
serial data stream on RX_IN. You can set the CRU to automatically or
manually alter the receiver PLL phase and frequency to match the bit
transition on the incoming data stream. This is to eliminate any
clock-to-data skew or to keep the receiver PLL locked to the reference
clock (lock-to-data or lock-to-reference mode). The CRU generates two
clocks, a high-speed RCVD_CLK to feed the deserializer and a low-speed
RCVD_CLK
to feed transceiver logic. You can set the CRU to optionally
detect run-length violations in the incoming data stream and generate an
error whenever the preset run length is exceeded (run-length violation
detection circuit).
Lock-to-Reference Mode & Lock-to-Data Mode
The Stratix GX device offers both automatic and manual locking options,
as described in the following sections.
Automatic Lock Mode
By default, the CRU initially locks to the CRU reference clock RX_CRUCLK
(lock-to-reference mode) until conditions warrant the switchover to the
incoming data (lock-to-data mode). The device switches to the
lock-to-data mode when the rx_freqlocked signal goes high. After
switching to lock-to-data mode, the CRU requires more time to lock to the
incoming serial data.
f
For information about the CRU to serial data lock time, which includes
frequency lock (during lock-to-reference mode) and phase lock (during
lock-to-data mode), refer to the Stratix GX FPGA Family data sheet. Also
refer to the Reset Control & Power Down chapter for the recommendations
on resets.
To automatically transition from the lock-to-reference mode to the
lock-to-data mode, the following conditions must be met:
■ The CRU PLL is within the prescribed PPM frequency threshold
setting (125, 250, 500, or 1,000 PPM) of the CRU reference clock.
■ Reference clock and CRU PLL output are phase matched (phases are
within 0.08 UI).