Altera Stratix GX Transceiver - Manual (Page 192)

6–38 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Design Example
Figure 6–33. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Summary
Design Example The design example shows the GigE synchronization sequence and
illustrates what happens when the receiver loses synchronization, as
described in clause 36 of the IEEE 802.3 specification. To simplify the
documentation process, the design is implemented in Verilog hardware
description language (HDL).
Design Description
When the protocol is specified as GigE, synchronization is achieved on
receiving three (/K28.5/, /Dx.y/) ordered sets. Each /K28.5/ is
separated by any odd number of /Dx.y/ code groups. Invalid code
groups are not supported during the synchronization stage. If at any time
four invalid code groups are received separated by fewer than three valid
code groups, synchronization is lost. This design example shows both the
transmission of the synchronization sequence and the transmission of the
invalid error codes that cause the loss of synchronization.
`define reset 3'd0
`define donothing 3'd1
`define sync 3'd2
`define tx_err 3'd3