Altera Stratix GX Transceiver - Manual (Page 280)

9–54 Altera Corporation
Stratix GX Transceiver User Guide January 2005
Recommended Resets
The waveform in Figure 9–16 shows the functionality of the transmitter
reset sequence shown in Figure 9–15 . As described in Table 9–1 on
page 9–3 , the pll_areset resets the entire transceiver block, including
both the analog and digital portions of the transmitter and receiver. After
this signal is deasserted, the controller waits until the transmitter PLL is
stable (pll_locked = 1'b1) before deasserting tx_digitalreset.
This ensures that the output of the transmitter PLL is stable before
releasing any of the logic that it feeds.
Figure 9–16. Transmitter Reset Sequence Waveform
Design Example 1
This design example shows a transmit-only configuration with inclk as
both the transmit PLL input reference clock and the transmit parallel
interface clock.
This design example has the following constraints:
■ If your design requirements are different from the examples, use the
flow charts and waveforms for each configuration as design
guidelines.
■ The design example requires a reset controller that generates a
sync_reset
(synchronous reset) for the entire system.
■ The design example has an async_reset (a power down in GXB
terms) and digital resets for transmit and receive. All user input
digital resets must be at least four cycles long.
■ This design example does not cover all the digital reset scenarios in
a system that resets the digital logic of the GXB.
■ In this example, whenever the rx_freqlocked signal toggles the
rxdigitalreset
, the receiver’s digital circuit is reset. However,
you can make changes to the design to avoid this if, for example, you
want to debug your design without the core being reset.
pll_areset
tx_digitalreset
pll_locked
Output Status
Reset Signals
Stable TXPLL Clock
1 2
3
4