Altera Stratix GX Transceiver - Manual (Page 317)

Altera Corporation C–7
January 2005 Stratix GX Transceiver User Guide
■ You can use the REFCLKB pin on an unused transceiver block to
bring in the clock. Altera recommends that you study the IQ routing
to ensure that the transceiver block to be used can be reached from
the selected REFCLKB pin. It might be possible to use the global clock
pin for lower input clock frequencies. If the design requires using
more than one transceiver block, there might be some restrictions
because of the limited global clock resources. Please refer to the
Stratix GX FPGA Family data sheet for more information on clocking
resources available for each device in the family.
■ For designs that have receive-only configurations, try these
solutions:
● While asserting rxanalogreset, ensure (if possible) that all
four channels are not being reset at the same time.
● Do not use the transmitter PLL, train receive PLL from the
receiver input reference clock (rx_cruclk).
You must carefully evaluate your design based on the recommendations
in this appendix. Because you can configure the Stratix GX device in
many different ways, there might be some configurations that are not
covered by this document. Please contact ALTERA Applications for
resolution on issues that are not addressed in this document.