Rainbow Electronics FARGO MAESTRO 100 (with TCP_IP) - Manual (Page 759)

APPENDIXES
Technical Appendixes
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WM_DEV_OAT_UGD_049 - 001 APPENDIXES August 23, 2007
3.2.3 Execution Conditions
Before reception of errors of §2.1, AT+CMUX=<mode>[,<subset>
[,<port_speed>[,<N1>[,<T1>[,<N2>[,<T2>[,<T3>]]]]]]] first reply OK.
3.2.4 Power Down Control (Sleep Mode)
CMUX feature is based on ETSI 27.010 specifications that provide Sleep-On/Wake-Up
procedure through 27.010 multiplexing protocol. It suits the description of the serial
port sleep mode mechanism (Please refer to §3.7 Specifications of Power Down
Control mechanism through serial Ports (physical Ù RS232 ports or virtual Ù CMUX
ports)).
To match sleep mode specifications (as specified in §3.7.4), Wavecom Wireless CPU ®
handles 27.010 MSC protocol frames that are dependent of each emulated port
(associated to a particular DLCI).
Ù Physical signals (such as DTR) of the UART on which it has been activated are not
monitored by Wavecom Wireless CPU ® (DCE).
To cope with Wavecom sleep mode, 27.010 sleep mode procedures are authorized
only when all activated emulated/virtual ports are in Serial Sleep mode state Ù
emulated application DTR and CTS are low on each port, no AT response is to be
sent…
CMUX wake-up/sleep-on frames as specified in 27.010 recommendations applies to
all activated DLC since those particular frames (PSC frames) are sent/received over the
DLCI 0, which is the control channel.
3.2.5 Sleep Mode Activation
For all opened DLCI, each connected application on each DLC should set its DTR low
in order to have the Wireless CPU
® sleep.
RX data line (DTE)
Not Clear to Send
Clear to Send
Busy
Ready
CTS (DTE e.g. logical MSC frame sent by the WAVECOM Wireless CPU ® )
DTR (DTE e.g. logical MSC frame through PC MUX driver)
1
2 3
1: The application (DTE) drops DTR to indicate a busy state (a protocol MSC frame is
sent by the PC CMUX driver on the concerned DLCI)
2: Wavecom Wireless CPU ® (DCE) checks if there are any pending AT response to
send.