Document Outline

• Stratix GX Transceiver User Guide
  • Contents
  • About This User Guide
    • How to Contact Altera
    • Typographic Conventions
  • 1. Introduction
    • Gigabit Transceiver Block Highlights
    • Transceiver Block Architecture
      • Analog Section Overview
        • Transmitter Differential I/O Buffers
        • Receiver Differential I/O Buffers
        • Transmitter & Receiver PLLs
        • Clock Recovery Unit
        • Serializer Deserializer (SERDES)
      • Digital Overview
        • Transmitter & Receiver Phase Compensation FIFO Buffer
        • Byte Serializer/Deserializer
        • 8B/10B Encoder/Decoder
        • Word Aligner
        • Channel Aligner
        • Rate Matcher
    • Modes of Operation
      • Basic Mode
      • SONET Mode
      • XAUI Mode
      • GigE Mode
      • Loopback
      • Built-In Self Test
  • 2. Stratix GX Analog Description
    • Introduction
    • Transmitter Analog
      • Transmitter Buffer
        • Programmable Voltage Output Differential (VOD)
        • Programmable Pre-Emphasis
        • Programmable Transmitter Termination
      • Transmitter PLL
        • Clock Synthesis
        • Transmitter PLL Bandwidth Setting
      • Serializer (Parallel-to-Serial Converter)
    • Receiver Analog
      • Receiver Input Buffer
        • Programmable Receiver Termination
        • Enable Stratix GX-to-Stratix GX Receiver DC Coupling
        • Equalizer Mode
      • Receiver PLL
        • Clock Synthesis
        • PPM Frequency Threshold Detector
        • Receiver Bandwidth Type
      • Clock Recovery Unit
        • Lock-to-Reference Mode & Lock-to-Data Mode
        • Run Length Violation Detection Circuit
      • Deserializer (Serial-to-Parallel Converter)
    • MegaWizard Analog Features
      • MegaWizard Analog Feature Considerations
  • 3. Basic Mode
    • Introduction
    • Basic Mode Receiver Architecture
      • Word Aligner
        • Pattern Detector Module
        • Manual Alignment Modes
      • 8B/10B Decoder
        • 10-bit Decoding
        • Reset
        • Code Error Detect
        • Disparity Error Detector
        • Control Detect
      • Byte Deserializer
      • Receiver Phase Compensation FIFO Buffer
    • Basic Mode Transmitter Architecture
      • Transmitter Phase Compensation FIFO Buffer
      • Byte Serializer
      • 8B/10B Encoder
        • 8B/10B Reset Condition
        • Control Code Encoding
    • Basic Mode Clocking
      • Basic Mode Channel Clocking
      • Basic Mode Inter-Transceiver Block Clocking
    • Basic Mode MegaWizard Plug-In
      • Basic Mode MegaWizard Plug-In Manager Considerations
      • Basic Mode altgxb MegaWizard Options
  • 4. SONET Mode
    • Introduction
    • SONET Mode Receiver Architecture
      • Word Aligner
        • Pattern Detector Module
      • Byte Deserializer
      • Receiver Phase Compensation FIFO Module
    • SONET Mode Transmitter Architecture
      • Transmitter Phase Compensation FIFO Buffer
      • Byte Serializer
    • SONET Mode Clocking
      • SONET Mode Channel Clocking
      • SONET Mode Inter-Transceiver Block Clocking
    • SONET Mode MegaWizard Plug-In Manager
      • SONET Mode MegaWizard Considerations
      • SONET Mode altgxb MegaWizard Options
  • 5. XAUI Mode
    • Introduction
    • XAUI Mode Receiver Architecture
      • Word Aligner
        • Pattern Detector Module
        • XAUI Synchronization Mode
      • Channel Aligner
      • Rate Matcher
      • 8B/10B Decoder
        • 10-Bit Decoding
        • Reset
        • Code Error Detect
        • Disparity Error Detector
        • Control Detect
      • PCS - XGMII Code Conversion
      • Byte Deserializer
      • Receiver Phase Compensation FIFO Module
    • XAUI Mode Transmitter Architecture
      • Transmitter Phase Compensation FIFO Module
      • Byte Serializer
      • XGMII Character to PCS Code-Group Mapping
      • 8B/10B Encoder
        • 8B/10B Reset Condition
        • Control Code Encoding
    • XAUI Mode Clocking
      • XAUI Mode Channel Clocking
      • XAUI Inter-Transceiver Block Clocking
    • XAUI Mode MegaWizard Plug-In Manager
      • XAUI Mode MegaWizard Considerations
      • XAUI Mode altgxb MegaWizard Options
  • 6. GigE Mode
    • Introduction
      • Word Aligner
        • Pattern Detector Module
        • Synchronization State Machines
      • Rate Matcher
      • 8B/10B Decoder
        • 10-Bit Decoding
        • Reset
        • Code Error Detect
        • Disparity Error Detector
        • Control Detect
      • Receiver Phase Compensation FIFO Buffer
    • GigE Mode Transmitter Architecture
      • Transmitter Phase Compensation FIFO Buffer
      • GigE Transmitter Synchronization
      • Idle Generation
      • 8B/10B Encoder
        • Reset
        • Control Code Encoding
    • GigE Mode Clocking
      • GigE Mode Channel Clocking
      • GigE Mode Inter-Transceiver Clocking
      • GigE Mode MegaWizard Considerations
      • GigE Mode altgxb MegaWizard Options
    • Design Example
      • Design Description
      • Simulation Waveform & Hardware Verification Results
  • 7. Loopback Modes
    • Introduction
    • Serial Loopback
    • Parallel Loopback
    • Reverse Serial Loopback
  • 8. Stratix GX Built-In Self Test (BIST)
    • Introduction
    • Pattern Generator
      • PRBS Mode Generator
      • Incremental Mode Generator
      • High-Frequency Mode Generator
      • Low-Frequency Mode Generator
      • Mix-Frequency Mode Generator
    • Pattern Verifier
      • PRBS Mode Verifier
      • Incremental Mode Verifier
    • Design Examples
      • Design 1: PRBS BIST Generator & Verification Design
        • Top-Level Design (PRBS.v)
        • Reset Module Design (reset_mod.v)
        • altgxb Instantiation (PRBS_BIST.v)
        • Results
      • Design 2: Incremental BIST Generator & Verification Design
        • Top-Level Design (Incremental)
        • Reset Module Design (reset_mod.v)
        • altgxb Instantiation (Incr_BIST.v)
        • Results
      • Design 3: High-Frequency Transmitter Generator Design
        • altgxb Instantiation (High_Freq_BIST.v)
        • Results
      • Design 4: Low-Frequency Transmitter Generator Design
        • altgxb Instantiation (low_freq_BIST.v)
        • Results
      • Design 5: Mix-Frequency Transmitter Generator Design
        • altgxb Instantiation (mix_freq_BIST.v)
        • Results
  • 9. Reset Control & Power Down
    • Introduction
    • Power On Reset (POR)
    • USER Reset & Enable Signals
    • Recommended Resets
      • Receiver & Transmitter Reset
        • Train Receive CRU With Transmit PLL Output Clock
        • Train Receive CRU With Transmit PLL Output Clock Option Disabled
      • Receiver Reset
        • Receive CRU With Transmit PLL Output Clock Option Enabled
        • Receive CRU With Transmit PLL Output Clock Option Disabled
      • Transmitter Reset
    • Power Down
  • Appendix A. Data & Control Codes
    • 8B/10B Code
      • Code Notation
      • Disparity Calculation
      • Supported Codes
  • Appendix B. Ports & Parameters
    • Input Ports
    • Output Ports
    • Parameter Descriptions
  • Appendix C. REFCLKB Pin Constraints
    • Known Issues
      • Quartus II Software Messages
        • Quartus II Software to Version 3.0 SP2
        • Quartus II Software Version 4.0
        • Quartus II Software Versions 4.0 SP1 & 4.1
      • Recommendations