Texas Instruments TMS320C3x - Manual (Page 104)

Instruction Cache
4-22
Only instructions may be fetched from the program cache. All reads and writes
of data in memory bypass the cache. Program fetches from internal memory
do not modify the cache and do not generate cache hits or misses. The pro-
gram cache is a single-access memory block. Dummy program fetches (for
example, those following a branch) are treated by the cache as valid program
fetches and can generate cache misses and cache updates.
Notes: Using Self-Modifying Code
Be careful when using self-modifying code. If an instruction resides in the
cache and the corresponding location in primary memory is modified, the
copy of the instruction in the cache is not modified.
You can use the cache more efficiently by aligning program code on 32-word
address boundaries. Do this with the .
align directive when coding assembly
language.
4.3.3 Cache Control Bits
Three cache control bits are located in the CPU status register:
- Cache Clear Bit (CC). Set CC = 1 to invalidate all entries in the cache. This
bit is always cleared after it is written to; it is always read as a 0. At reset,
the cache is cleared, and 0 is written to this bit.
- Cache Enable Bit (CE). Set CE = 1 to enable the cache, allowing the
cache to be used according to the LRU cache algorithm. Set CE = 0 to dis-
able the cache; this prevents cache update modifications (thus, no cache
fetches can be made). At reset, 0 is written to this bit. Cache clearing (CC
= 1) is allowed when CE = 0.
- Cache Freeze Bit (CF). Set CF = 1 to freeze both the cache and LRU
stack manipulation. If the cache is enabled (CE = 1) and the cache is
frozen (CF = 1), fetches from the cache are allowed, but modification of
cache contents is not allowed. Cache clearing (CC = 1) is allowed when
CF = 1 or CF = 0. At reset, this CF bit is cleared to 0.
Table 4–1 shows the combined effect of the CE and CF.