Texas Instruments TMS320C3x - Manual (Page 312)

Configuration
10-9 TMS320C32 Enhanced External Memory Interface
The instruction immediately preceding a change in the data-size or
memory-width bit fields should not perform a multicycle store. Do
not follow a change in the data-size or memory-width bit fields with
a store instruction. Also, do not perform a load in the next two
instructions following a change in the data-size or memory-width
bit fields
10.3.1.3 IOSTRB Control Register
The IOSTRB control register (Figure 10–6) is a 32-bit register that contains the
control bits for the portion of the external bus memory space that is mapped to
IOSTRB. Unlike the STRB0 and STRB1, there is no byte-enable signal for the
IOSTRB. The data access through the IOSTRB is always 32-bit. The following
table lists the register bits with the bit names and functions. At the system reset,
0F8h is written to the IOSTRB control register. The IOSTRB timing is identical
to the ‘C30 IOSTRB timing.
Figure 10–6. IOSTRB Control Register
ББ
ББ
БББББ
БББББ
31 16
ББББББ
ББББББ
15 12
ББББББ
ББББББ
11 8
БББББ
БББББ
7 5
ББББББ
ББББББ
4 3
ББББББ
ББББББ
2 0
Б
Б ББ
ББ
xx xx xx WTCNT SWW xx
Б
Б ББ
ББ
БББББ
БББББ
ББББББ
ББББББ
ББББББ
ББББББ
БББББ
БББББ
R/W ББББББ
ББББББ
R/W ББББББ
ББББББ
Б
Б Notes: 1) R = read, W = write
2) xx = reserved, read as 0
Note:
After changing the bit fields of the IOSTRB control register, up to three
instructions are fetched before the IOSTRB bus is reconfigured.