Texas Instruments TMS320C3x - Manual (Page 442)

DMA Controller
12-63 Peripherals
12.3.5.2 Rotating Priority Scheme
In a rotating priority scheme, the last channel serviced becomes the lowest
priority channel. The other channel sequentially rotates through the priority list
with the lowest channel next to the last-serviced channel becoming the highest
priority on the following request. The priority rotates every time the channel
most recently granted priority completes its access. At system reset, the
channels are ordered from highest to lowest priority (0, 1).
To select this scheme, set the PRIORITY MODE bit (bit 14) of channel 0’s DMA
control register to 0.
12.3.6 CPU and DMA Controller Arbitration
The DMA controller transfers data on its own internal buses. Arbitration is neces-
sary only when a resource conflict exists between the DMA controller and the
CPU. The arbitration causes no delay. When there is no conflict, the CPU and
DMA controller accesses proceed in parallel.
All arbitration between the CPU and the DMA controller is on an access basis.
DMA controller internal memory access starts during H3 (see Section 8.5,
Clocking Memory Access, for more information).
When the CPU and DMA controllers request the same resource, priority is
determined as follows:
- For the ‘C30 and ‘C31, the CPU always has higher priority, thus the DMA
must wait until the CPU frees the resource.
- For the ‘C32, the DMA channel’s DMA PRI bits (bits 12 and 13 of the channel
control register) define the arbitration rules (as shown in Table 12–8). The
CPU has higher priority than the DMA when DMA PRI = 00
2
; it has lower
priority than the DMA when DMA PRI = 11
2
. They rotate priority when DMA
PRI = 01
2
.