Texas Instruments TMS320C3x - Manual (Page 493)

Individual Instructions
13-35 Assembly Language Instructions
- Empty expressions are not allowed for the displacement in indirect mode:
LDI *+AR0(),R0 is not legal.
- You can precede long immediate mode operands (destination of BR and
CALL) with an @ sign:
BR label can be written as BR @label
- You can use the LDP pseudo-op to load a register (usually DP) with the
eight most significant bits (MSBs) of a relocatable address:
LDP addr,REG or LDP @addr,REG
The @ sign is optional.
If the destination register is the DP, you can omit the DP in the operand. LDP
generates an LDI instruction with an immediate operand and a special relo-
cation type.
- You can write parallel instructions in either order. For example:
ADDI can be written as STI
|| STI || ADDI
- You can write the parallel bars indicating part 2 of a parallel instruction
anywhere on the line from column 0 to the mnemonic. For example:
ADDI can be written as ADDI
|| STI || STI
- If the second operand of a parallel instruction is the same as the third (desti-
nation register) operand, you can omit the third operand. This allows you to
write 3-operand parallel instructions that look like normal 2-operand instruc-
tions. For example,
ADDI *AR0,R2,R2 can be written as ADD *AR0,R2
|| MPYI *AR1,R0,R0 || MPYI *AR1,R0
Instructions affected (applies to all parallel instructions that have a register
second operand): ADDI, ADDF, AND, MPYI, MPYF, OR, SUBI, SUBF,
XOR.
- You can write all commutative operations in parallel instructions in either
order. For example, you can write the ADDI part of a parallel instruction in
either of two ways:
ADDI *AR0,R1,R2 or ADDI R1,*AR0,R2
Instructions affected include: parallel instructions containing any of the
following: ADDI, ADDF, MPYI, MPYF, AND, OR, XOR.