Condition codes and flags – Texas Instruments TMS320C3x User Manual

Page 486

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Condition Codes and Flags

13-28

13.5 Condition Codes and Flags

The ’C3x provides 20 condition codes (00000–10100, excluding 01011) that
you can place in the

cond field of any of the conditional instructions, such as

RETS

cond or LDFcond. The conditions include signed and unsigned compari-

sons, comparisons to 0, and comparisons based on the status of individual
condition flags. All conditional instructions can accept the suffix U to indicate
unconditional operation.

Seven condition flags provide information about properties of the result of
arithmetic and logical instructions. The condition flags are stored in the status
register (ST) and are affected by an instruction only when either of the following
two cases occurs:

-

The destination register is one of the extended-precision registers
(R7–R0). (This allows for modification of the registers used for addressing
but does not affect the condition flags during computation.)

-

The instruction is one of the compare instructions (CMPF, CMPF3, CMPI,
CMPI3, TSTB, or TSTB3). (This makes it possible to set the condition flags
according to the contents of any of the CPU registers.)

The condition flags are modified by most instructions when either of the pre-
ceding conditions is established and either of the following two cases occurs:

-

A result is generated when the specified operation is performed to infinite
precision. This is appropriate for compare and test instructions that do not
store results in a register. It is also appropriate for arithmetic instructions
that produce underflow or overflow.

-

The output is written to the destination register, as shown in Table 13–11.
This is appropriate for other instructions that modify the condition flags.

Table 13–11. Output Value Formats

Type of Operation

Output Format

Floating point

8-bit exponent, one sign bit, 31-bit fraction

Integer

32-bit integer

Logical

32-bit unsigned integer

Figure 13–6 shows the condition flags in the low-order bits of the status register.
Following the figure is a list of status register condition flags with a description
of how the flags are set by most instructions. For specific details of the effect of
a particular instruction on the condition flags, see the description of that instruc-
tion in Section 13.6,

Individual Instruction Descriptions, on page 13-32.

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