Texas Instruments TMS320C3x - Manual (Page 240)

Pipeline Conflicts
8-4
8.2 Pipeline Conflicts
Pipeline conflicts in the ’C3x can be grouped into the following categories:
Branch conflicts Branch conflicts involve most of those instructions or
operations that read and/or modify the PC.
Register conflicts Register conflicts involve delays that can occur when
reading from, or writing to, registers that are used for
address generation.
Memory conflicts Memory conflicts occur when the internal units of the
’C3x compete for memory resources.
Each of these three types, including examples, is discussed in the following
subsections. In these examples, when data is refetched or an operation is
repeated, the symbol representing the stage of the pipeline is appended with
a number. For example, if a fetch is performed again, the instruction mnemonic
is repeated. When an access is detained for multiple cycles because the unit
is not ready, the symbol RDY indicates that a unit is not ready and RDY indi-
cates that a unit is ready. If the particular unit does not perform a function, the
nop label is placed in that stage of the pipeline.
8.2.1 Branch Conflicts
The first class of pipeline conflicts occurs with standard (nondelayed)
branches, that is, BR, B
cond, DBcond, CALL, IDLE, RPTB, RPTS, RETIcond,
RETS cond, interrupts, and reset. Conflicts arise with these instructions and
operations because, during their execution, the pipeline is used only for the
completion of the operation; other information fetched into the pipeline is dis-
carded or refetched, or the pipeline is inactive. This is referred to as flushing
the pipeline. Flushing the pipeline is necessary in these cases to ensure that
portions of succeeding instructions do not inadvertently get partially executed.
TRAP
cond and CALLcond are classified differently from the other types of
branches and are considered later.
Example 8–1 shows the code and pipeline operation for a standard branch.
Note: Dummy Fetch
In this example, one dummy fetch (an MPYF instruction) is performed before
the branch is decoded. After the branch address is available, a new fetch (an
OR instruction) is performed.