Texas Instruments TMS320C3x - Manual (Page 226)

DMA Interrupts
7-42
Table 7–9. Pipeline Operation with PUSH ST
Cycle Description Fetch Decode Read Execute
1 NOP
2 LDI NOP
3 MPYI LDI NOP
4 Read location V_ADDR PUSH MPYI LDI NOP
5 Load AR1; recognize interrupt – PUSH MPYI LDI
6 Clear GIE bit; clear interrupt flag; read SP Interrupt PUSH MPYI
7 Read interrupt vector table; save ST in stack Interrupt PUSH
8 Store return address on stack Interrupt
The following example shows setting the GIE bit by a load instruction that is
immediately followed by an interrupt:
... ; GIE = 1
LDI 02000h, ST ; GIE = 0
interrupt recognized ––>MPYI *AR1, R0 ;
ADD *AR0, R1
In this example, the load of the status register or interrupt-flag register overwrites
the reset of the GIE bit by the interrupt (see Table 7–10).
Table 7–10. Pipeline Operation with Load Followed by Interrupt
Cycle Description Fetch Decode Read Execute
1 LDI
2 Interrupt recognized – LDI
3 Interrupt resets GIE bit, clears interrupt flag,
reads SP interrupt LDI
4 GIE set by load instruction; interrupt vector table
read and ST saved on stack interrupt LDI
5 Store return address on stack interrupt
6 Fetch first instruction of ISR with GIE = 1 ISR
A similar situation may occur if the GIE bit = 1 and an instruction executes that
is intended to modify the other status bits and leave the GIE bit set. In the above
example, this erroneous setting would occur if the interrupt were recognized two
cycles before the POP ST instruction. In that case, the interrupt would clear the
GIE bit, but the execution of the POP instruction would set the GIE bit. Since the
interrupt has been recognized, the interrupt service routine will be entered with
interrupts enabled, rather than disabled as expected.