Texas Instruments TMS320C3x - Manual (Page 263)

2-cycle dummy
load of src2
R0, *AR6 until the
store is complete
actual read of
src2 and src1
Clocking Memory Accesses
8-27 Pipeline Operation
Example 8–17. Dummy sr2 Read
STI R0,*AR6 ; AR6 points to MSTRB space
ADDI3 *AR1,*AR3,R0 ; AR3 points to on-chip RAM ( src 1)
; AR1 points to MSTRB space ( src 2)
H1
H3
Pipeline Operation
PC Fetch Decode Read Execute
n STI
n+1 ADDI3 STI
n+2 ADDI3 STI
n+3 — STI
n+4 — —
n+5 ADDI3 —
n+6 — —
n+7 ADDI3 —
n+8 ADDI3
Two cycles are required for the MSTRB store. Two additional cycles are required
for the dummy MSTRB read of *AR3 (because a read follows a write). One cycle
is required for an actual MSTRB read of *AR3.