Texas Instruments TMS320C3x - Manual (Page 532)

ASH3 Arithmetic Shift, 3-Operand
13-74
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM Operation is not affected by OVM bit value.
Example 1 ASH3 *AR3 – – (1),R5,R0
Before Instruction After Instruction
R0 00 0000 0000 R0 00 02B0 0000
R5 00 0000 02B0 R5 00 0000 02B0
AR3 80 9921 AR3 80 9920
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809921h 10 809921h 10 16 16
Mode Bit