Texas Instruments TMS320C3x - Manual (Page 366)

TMS320C31 Boot Loader
11-11 Using the TMS320C31 and TMS320C32 Boot Loaders
11.1.4.2 Serial-Port Loading
Boot loads, by way of the ’C31 serial port, are selected by driving the INT3 pin
active (low) following reset. The loader automatically configures the serial port
for 32-bit fixed-burst-mode reads. It is interrupt-driven by the frame synchro-
nization receive (FSR) signal. You cannot change this mode for boot loads.
Your hardware must generate the serial-port clock and FSR externally.
As with memory loads, a header must precede the actual program to be loaded.
However, you need only supply the block size and destination address because
the loader and your hardware have predefined serial-port speed and data format
(that is, skip data words 0 and 1).
The transferred data-bit order must begin with the MSB and end with the LSB.
11.1.5 Interrupt and Trap-Vector Mapping
Unlike the microprocessor mode, the microcomputer/boot-loader (MCBL)
mode uses a dual-vectoring scheme to service interrupt and trap requests. Dual
vectoring was implemented to ensure code compatibility with future versions of
’C3x devices.
In a dual-vectoring scheme, branch instructions to an address, rather than
direct-interrupt vectoring, are used. The normal interrupt and trap vectors are
defined to vector to the last 63 locations in the on-chip RAM, starting at address
809FC1h. When the loader is invoked, the interrupt vector table is remapped
by the processor to the last 63 locations in RAM block 1 of the ’C31. These
locations are assumed to contain branch instructions to the interrupt source
routines.
Make sure that these locations are not inadvertently overwritten by
loaded program or data values.
Table 11–6 shows the MCBL/MP mode interrupt and trap instruction memory
maps.