Trapcond – Texas Instruments TMS320C3x User Manual
Page 701
Trap Conditionally
TRAPcond
13-243
Assembly Language Instructions
Syntax
TRAP
cond N
Operation
0
→
ST(GIE)
If
cond is true:
Next PC
→
*++SP,
Trap vector N
→
PC.
Else:
Set ST(GIE) to original state.
Continue.
Operands
N (0
≤
N
≤
31)
Opcode
31
24 23
16
8 7
0
15
0 1 1 1 0
0
0
0
1
cond
0 0
0 0 0 0 0 0 0 0 0 0 1
N + 20h
Description
Interrupts are disabled globally when 0 is written to ST(GIE). If the condition
is true, the contents of the PC are pushed onto the system stack, and the PC
is loaded with the contents of the specified trap vector (N). If the condition is
not true, ST(GIE) is set to its value before the TRAP
cond instruction changes
it.
The ’C3x provides 20 condition codes that can be used with this instruction
(see Table 13–12 on page 13-30 for a list of condition mnemonics, condition
codes, and flags). Condition flags are set on a previous instruction only when
the destination register is one of the extended-precision registers (R7–R0) or
when one of the compare instructions (CMPF, CMPF3, CMPI, CMPI3, TSTB,
or TSTB3) is executed.
Cycles
5
Status Bits
LUF
Unaffected
LV
Unaffected
UF
Unaffected
N
Unaffected
Z
Unaffected
V
Unaffected
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Mode Bit