Texas Instruments TMS320C3x - Manual (Page 437)

DMA Controller
12-58
12.3.3.3 Transfer-Counter Register
The transfer-counter register is a 24-bit register that contains the number of
words to be transmitted. Figure 12–40 shows the transfer-counter operation.
It is controlled by a 24-bit counter that decrements at the beginning of a DMA
memory write. In this way, it can control the size of a block of data transferred.
The transfer-counter register is set to 0 at system reset. When the TCINT bit
of the DMA global-control register is set, the transfer-counter register causes
a DMA interrupt flag to be set when 0 is reached.
The counter is decremented after completing the destination-address fetch.
The interrupt is generated after the transfer counter is decremented and after
the completion of the write of the last transfer.
The decrementer checks whether the transfer counter equals 0 after the decre-
ment is performed. As a result, if the counter register has a value of 1, then the
DMA channel can be halted after only one transfer is performed. Thus, by set-
ting the transfer counter to 1, the DMA channel transfers the minimum possible
number of words (1 time). The value of the transfer counter is treated as an un-
signed integer. Transfers can be halted when a 0 value is detected after a decre-
ment. If the DMA controller channel is not halted after the transfer reaches zero,
the counter continues decrementing below 0. Thus, by setting the transfer
counter to 0, the DMA channel transfers the maximum possible number of
words (100 0000h times).