Texas Instruments TMS320C3x - Manual (Page 529)

Arithmetic Shift ASH
13-71 Assembly Language Instructions
Syntax ASH count, dst
Operation If ( count
≥
0):
dst << count
→
dst
Else:
dst >> |count |
→
dst
Operands count general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 0 0 1 dst count 1 1 G
Description The seven LSBs of the count operand are used to generate the 2s-comple-
ment shift count of up to 32 bits.
If the count operand is greater than 0, the dst operand is left shifted by the value
of the count operand. Low-order bits that are shifted in are zero filled, and high-
order bits are shifted out through the carry (C) bit.
Arithmetic left shift:
C
←
dst
←
0
If the count operand is less than 0, the dst operand is right shifted by the abso-
lute value of the count operand. The high-order bits of the dst operand are sign-
extended as it is right shifted. Low-order bits are shifted out through the C bit.
Arithmetic right shift:
sign of dst
→
dst
→
C
If the count operand is 0, no shift is performed, and the C bit is set to 0. The
count and dst operands are assumed to be signed integers.
Cycles 1