Texas Instruments TMS320C3x - Manual (Page 559)

Parallel FIX and STI FIX||STI
13-101 Assembly Language Instructions
Syntax FIX src2, dst1
|| STI src3, dst2
Operation fix( src2 )
→
dst1
|| src3
→
dst2
Operands src2 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
- ’C31 silicon revision 6.0 or greater
- ’C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n1, 0
≤
n1
≤
7)
src3 register (R n2, 0
≤
n2
≤
7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
1 1 0 1 0 1 dst1 src2 dst2 0 src3 0 0 0
Description A floating-point-to-integer conversion is performed. All registers are read at
the beginning and loaded at the end of the execute cycle. This means that, if
one of the parallel operations (STI) reads from a register, and the operation
being performed in parallel (FIX) writes to the same register, STI accepts the
contents of the register as input before it is modified by FIX.
If src2 and dst2 point to the same location, src2 is read before the write to dst2.
Integer overflow occurs when the floating-point number is too large to be rep-
resented as a 32-bit 2s-complement integer. In the case of integer overflow,
the result is saturated in the direction of overflow.
Cycles 1