Texas Instruments TMS320C3x - Manual (Page 238)

Perfect
overlap
Pipeline Structure
8-2
8.1 Pipeline Structure
The following list describes the four major units of the ‘C3x pipeline structure and
their functions:
Fetch unit (F) Fetches the instruction words from memory
and updates the program counter (PC).
Decode unit (D) Decodes the instruction word and performs
address generation. Also, the decode unit controls
modification of the AR
n registers in the indirect
addressing mode and of the stack pointer when
PUSH to/POP from the stack occurs.
Read unit (R) If required, reads the operands from memory.
Execute unit (E) If required, reads the operands from the register
file, performs the necessary operation, and writes
results to the register file. If required, results of
previous operations are written to memory.
All instruction executions perform these four basic functions: fetch, decode, read,
and execute. Figure 8–1 illustrates these four levels of the pipeline structure. The
levels are indexed according to instruction and execution cycle. In the figure, per-
fect overlap in the pipeline, where all four units operate in parallel, occurs at cycle
(
m). Levels about to be executed are at m +1, and those just previously executed
are at m–1. The ‘C3x pipeline controller supports a high-speed processing rate
of one execution per cycle. It also manages pipeline conflicts so that they are
transparent to you. You do not need to take any special precautions to ensure
correct operation.
Figure 8–1. TMS320C3x Pipeline Structure
CYCLE Fetch Decode Read Execute
m–3 W — — —
m–2 X W — —
m–1 Y X W —
m Z Y X W
m+1 — Z Y X
m+2 — — Z Y
m+3 — — — Z
Note: W, X, Y, Z = Instruction representations