Mpyf – Texas Instruments TMS320C3x User Manual
Page 604
MPYF
Multiply Floating-Point Value
13-146
Syntax
MPYF
src, dst
Operation
dst
×
src
→
dst
Operands
src general addressing modes (G):
0 0
register (R
n, 0
≤
n
≤
7)
0 1
direct
1 0
indirect (disp = 0–255, IR0, IR1)
1 1
immediate
dst register
(R
n, 0
≤
n
≤
7)
Opcode
31
24 23
16
8 7
0
15
0 0 0
0 1
0
1
0
0
dst
G
src
Description
The product of the
dst and src operands is loaded into the dst register. The src
operand is assumed to be a single-precision floating-point number, and the
dst
operand is an extended-precision floating-point number.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
1 if a floating-point underflow occurs; unchanged otherwise
LV
1 if a floating-point overflow occurs; unchanged otherwise
UF
1 if a floating-point underflow occurs; 0 otherwise
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if a floating-point overflow occurs; 0 otherwise
C
Unaffected
OVM
Operation is not affected by OVM bit value.
Example
MPYF R0,R2
Before Instruction
After Instruction
R0
07 0C80 0000
R0
07 0C80 0000
R2
03 4C20 0000
R2
0A 600F 2000
LUF
0
LUF
0
LV
0
LV
0
UF
0
UF
0
N
0
N
0
Z
0
Z
0
V
0
V
0
C
0
C
0
1.27578125e+01
1.4050e+02
1.79247266e+03
1.4050e+02
Mode Bit