Texas Instruments TMS320C3x - Manual (Page 575)

Load Floating-Point Value, Interlocked LDFI
13-117 Assembly Language Instructions
Syntax LDFI src, dst
Operation Signal interlocked operation
src
→
dst
Operands src general addressing modes (G):
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
dst register (Rn, 0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 0 1 1 1 1 dst src G
Description The src operand is loaded into the dst register. An interlocked operation is sig-
naled over XF0 and XF1. The src and dst operands are assumed to be floating-
point numbers. Only direct and indirect modes are allowed. See Section 7.4,
Interlocked Operations, on page 7-13 for a detailed description.
Cycles 1 if XF1 = 0 (see Section 7.4 on page 7-13)
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit