Texas Instruments TMS320C3x - Manual (Page 233)

Power Management Modes
7-49 Program Flow Control
7.9 Power Management Modes
The following ’C3x devices have been enhanced by the addition of two power-
down modes: IDLE2 and LOPOWER:
- ’C30 silicon version 7.0 or greater
- ’LC31
- ’C31 silicon revision 5.0 or greater
- ’C32
7.9.1 IDLE2 Power-Down Mode
The H1 instruction clock is held high until one of the four external interrupts is
asserted. In IDLE2 mode, the ’C3x devices supporting these modes behave as
follows:
- No instructions are executed.
- The CPU, peripherals, and internal memory retain their previous states.
- The external bus output pins are idle:
J The address lines remain in their previous states.
J The data lines are in the high-impedance state.
J The output control signals are in their inactive state.
J If a multicycle read or write does not preceed the IDLE2 opcode, that
access will be forzen onto the bus until IDLE2 is exited. This can be
advantageous for low power applications since the bus is frozen in an
active state. That is, the device pins are not floating, and therefore do
not require pullup or pulldowns.
- When the device is in the functional (nonemulation) mode, the clocks stop
with H1 high and H3 low (see Figure 7–11).
- The devices remain in IDLE2 until one of the four external interrupts
(INT3–INT0) is asserted for at least one H1 cycle. When one of the four
interrupts is asserted, the clocks start after a delay of one H1 cycle. When
the clocks restart, they may be in the opposite phase (that is, H1 may be
high if H3 was high before the clocks were stopped; H3 may be low if H1
was previously low). The H1 and H3 clocks remain 180 degrees out of
phase with each other (see Figure 7–12).
- During IDLE2 operations, the CPU recognizes one of the four external
interrupts if it is asserted for more than one H1 cycle. To avoid generating
multiple false interrupts in level-triggered mode, the interrupt must be
asserted for fewer than three H1 cycles.