Texas Instruments TMS320C3x - Manual (Page 542)

BRD Branch Unconditionally (Delayed)
13-84
Syntax BRD src
Operation src
→
PC
Operands src long-immediate addressing mode
Opcode
31 24 23 16 8 7 0 15
0 1 1 0 0 1 0 0 src
Description BRD signifies a delayed branch that allows the three instructions after the
delayed branch to be fetched before the PC is modified. The effect is a
single-cycle branch.
An unconditional branch is performed. The src operand is assumed to be a
24-bit unsigned integer. Note that bit 24 = 1 for a delayed branch.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example BRD 2Ch
Before Instruction After Instruction
PC 001B PC 002C
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Mode Bit