Texas Instruments TMS320C3x - Manual (Page 451)

DMA
Controller
12-72
Figure 12–49. DMA Timing When Destination is an IOSTRB Bus
Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source on chip R1 R2 R3 R4 R5
Destination IOSTRB
W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 W4 W4 W4 W4
1 + (2 + Cw) T Destination IOSTRB
Cw Cw Cw Cw
1 + (2 + Cw) T
(’C30 only)
Source STRB bus
R1 R1 R1 I R2 R2 R2 I R3 R3 R3 I
Cr Cr Cr (2 + Cr + 2 + C w) + (2 + C w +
max (1, Cr – C w + 1)) ( T – 1)
Destination IOSTRB bus
W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3
max (1, Cr – C w + 1)) ( T – 1)
Destination IOSTRB bus
Cw Cw Cw
Source STRB0, STRB1,
MSTRB bus
R1 R1 R1 I R2 R2 R2 I
Cr Cr
(2 C 2 C ) T ( T 1)
{
Destination IOSTRB W1 W1 W1 W1 W2 W2 W2 W2
(2 + C r + 2 + C w) T + ( T –1)
{
Cw Cw
Legend:
T = Number of transfers W = Single-cycle writes
Cr = Source-read wait states R n = Multicycle reads
Cw = Destination-write wait states W n = Multicycle writes
R = Single-cycle reads I = Internal register cycle
† Write followed by read incurs in one extra cycle.