Texas Instruments TMS320C3x - Manual (Page 693)

Subtract Integer, 3-Operand SUBI3
13-235 Assembly Language Instructions
Syntax SUBI3 src2, src1, dst
Operation src1 – src2
→
dst
Operands src1 3-operand addressing modes (T):
0 0 register (R n1, 0
≤
n1
≤
27)
0 1 indirect ( disp = 0, 1, IR0, IR1)
1 0 register (R n1, 0
≤
n1
≤
27)
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 register (R n2, 0
≤
n2
≤
27)
0 1 register (R n2, 0
≤
n2
≤
27)
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (Rn, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 1 0 0 1 1 0 1 dst T src1 src2
Description The difference between the src1 operand and the src2 operand is loaded into
the dst register. The src1, src2, and dst operands are assumed to be signed
integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C 1 if a borrow occurs; 0 otherwise
OVM Operation is affected by OVM bit value. Mode Bit