Texas Instruments TMS320C3x - Manual (Page 260)

Clocking Memory Accesses
8-24
8.5 Clocking Memory Accesses
This section discusses the role of internal clock phases (H1 and H3) and how
the ’C3x handles multiple-memory accesses. The previous section discusses
the interaction between sequences of instructions; this section discusses the
flow of data on an individual instruction basis.
Each major clock period of 33.3 ns is composed of two minor clock periods of
16.67 ns, labeled H3 and H1. The active clock period for H3 and H1 is the time
when that signal is high. See Figure 8–2.
Figure 8–2. Minor Clock Periods
H1
H3
Major clock period
H1
minor
clock period
H3
minor
clock period
The precise operation of memory reads and writes can be defined according
to these minor clock periods. The types of memory operations that can occur
are program fetches, data loads and stores, and DMA accesses.
8.5.1 Program Fetches
Internal program fetches are always performed during H3 unless a single data
store must occur at the same time due to another instruction in the pipeline. In that
case, the program fetch occurs during H1 and the data store occurs during H3.
External program fetches always start at the beginning of H3 with the address
being presented on the external bus. At the end of H1, the fetches are completed
with the latching of the instruction word.
8.5.2 Data Loads and Stores
Four types of instructions perform loads, memory reads, and stores:
- 2-operand instructions
- 3-operand instructions
- Multiplier/ALU operation with store instructions
- Parallel multiply and add instructions