Texas Instruments TMS320C3x - Manual (Page 282)

External Memory Interface Timing
9-16
The (M)STRB signal is low for the active portion of both reads and writes. The
active portion lasts one H1 cycle. Additionally, before and after the active portion
((M)STRB low) of writes only, there is a transition cycle of H1. This transition
cycle consists of the following sequence:
1) (M)STRB is high.
2) If required, (X)R/W changes state on H1 rising.
3) If required, address changes on H1 rising if the previous H1 cycle was the
active portion of a write. If the previous H1 cycle was a read, address
changes on the next H1 falling.
Figure 9–6 illustrates a read-read-write sequence for (M)STRB active and no
wait states. The data is read as late in the cycle as possible to allow maximum
access time from address valid. Although external writes require two cycles,
internally (from the perspective of the CPU and DMA) they require only one
cycle if no accesses to that interface are in progress. In the typical timing for
all external interfaces, the (X)R/W strobe does not change until (M)STRB or
IOSTRB goes inactive.