Texas Instruments TMS320C3x - Manual (Page 193)

Delayed Branches
7-9 Program Flow Control
7.2 Delayed Branches
The ’C3x offers three main types of branching: standard, delayed, and condi-
tional delayed.
Standard branches empty the pipeline before performing the branch, ensuring
correct management of the program counter and resulting in a ’C3x branch
taking four cycles. Included in this class are repeats, calls, returns, and traps.
Delayed branches on the ’C3x do not empty the pipeline, but rather execute
the next three instructions before the program counter is modified by the
branch. This results in a branch that requires only a single cycle, making the
speed of the delayed branch very close to that of the optimal block repeat
modes of the ’C3x. However, unlike block-repeat modes, delayed branches
may be used in situations other than looping. Every delayed branch has a stan-
dard branch counterpart that is used when a delayed branch cannot be used.
The delayed branches of the ’C3x are B
cond D, BRD, and DBcond D.
Conditional delayed branches use the conditions that exist at the end of the
instruction immediately preceding the delayed branch. They do not depend on
the instructions following the delayed branch. The condition flags are set by a
previous instruction only when the destination register is one of the extended-
precision registers (R0–R7) or when one of the compare instructions (CMPF,
CMPF3, CMPI, CMPI3, TSTB, or TSTB3) is executed. Delayed branches
guarantee that the next three instructions will execute, regardless of other
pipeline conflicts.
When a delayed branch is fetched, it remains pending until the three subsequent
instructions are executed. The following instructions cannot be used in the three
instructions after a delayed branch (see Example 7–6):
B cond DB cond D
B cond D IDLE
IDLE2
BR RETI cond
BRD RETS cond
CALL RPTB
CALL cond RPTS
DB cond TRAP cond
Delayed branches disable interrupts until the completion of the three instruc-
tions that follow the delayed branch regardless of whether the branch is or is
not performed.
Note: Incorrect Use of Delayed Branches
If delayed branches are used incorrectly, the PC is undefined.