Texas Instruments TMS320C3x - Manual (Page 447)

DMA Controller
12-68
The data transfer rate for a DMA channel (assuming a single-channel access
with no conflicts between CPU or other DMA channels) is as follows:
- On-chip memory and peripheral
J DMA read: One cycle
J DMA write: One cycle
- External memory (STRB, STRB0, STRB1, MSTRB)
J DMA read: Two cycles (one cycle external read followed by one
cycle load of internal DMA register)
J DMA write: Two cycles (identical to CPU write)
- External memory (IOSTRB)
J DMA read: Three cycles (two-cycle external read followed by one
cycle load of internal DMA register)
J DMA write: Two cycles (identical to CPU write)
If the DMA started and is transferring data over either external bus, do not
modify the bus-control register associated with that bus. If you must modify the
bus-control register (see Chapter 9 or 10), stop the DMA, make the modifica-
tion, and then restart the DMA. Failure to do this may produce an unexpected
zero-wait-state bus access.
DMA memory transfer timing can be very complicated, especially if bus resource
conflicts occur. However, some rules help you calculate the transfer timing for
certain DMA setups. For simplification, the following section focuses on a single-
channel DMA memory transfer timing with no conflict with the CPU or other
DMA channels. You can obtain the actual DMA transfer timing by combining the
calculations for single-channel DMA transfer timing with those for bus resource
conflict situations.
12.3.8.1 Single DMA Memory Transfer Timing
When the DMA memory transfer has no conflict with the CPU or any other
DMA channels, the number of cycles of a DMA transfer depends on whether
the source and destination location are designated as on-chip memory,
peripheral, or external ports. When the external port is used, the DMA transfer
speed is affected by two factors: the external bus wait state and the read/write
conflict (for example, if a write is followed by a read, the read takes one extra
half-cycle. See Figure 12–48 footnote on page 12-70). Figure 12–47 through
Figure 12–49 show the number of cycles a DMA transfer requires from different
sources to different destinations. Entries in the table represent the number of
cycles required to do the
T transfers, assuming that there are no pipeline conflicts.
A timing diagram for the DMA transfers accompanies each figure.