Texas Instruments TMS320C3x - Manual (Page 708)

XOR3 Bitwise-Exclusive OR, 3-Operand
13-250
Syntax XOR3 src2, src1, dst
Operation src1 XOR src2
→
dst
Operands src1 3-operand addressing modes (T):
0 0 register (R n1, 0
≤
n1
≤
27)
0 1 indirect ( disp = 0, 1, IR0, IR1)
1 0 register (R n1, 0
≤
n1
≤
27)
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 register (R n2, 0
≤
n2
≤
27)
0 1 register (R n2, 0
≤
n2
≤
27)
1 0 indirect ( disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (Rn, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 1 0 1 0 0 0 0 dst T src1 src2
Description The bitwise-exclusive OR between the src1 and src2 operands is loaded into
the dst register. The src1, src2, and dst operands are assumed to be unsigned
integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit